1. Field of the Invention
The present invention relates to non-volatile memory.
2. Description of the Related Art
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some EEPROM and flash memory devices have storage elements which use a floating gate to store two ranges of charges and, therefore, can be programmed/erased between two states, e.g., an erased state and a programmed state. Such a flash memory device is sometimes referred to as a binary flash memory device because each storage element can store one bit of data.
A multi-state (also called multi-level) flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, each storage element can store two bits of data when the storage element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges.
Typically, a program voltage (Vpgm) applied to the control gate during a program operation is applied as a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.4 V. Vpgm can be applied to the control gates of flash storage elements. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each storage element of a set of storage elements being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the storage element is being programmed. For arrays of multi-state flash storage elements, a verification step may be performed for each state of an storage element to determine whether the storage element has reached its data-associated verify level. For example, a multi-state storage element capable of storing data in four states may need to perform verify operations for three compare points.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically the program voltage is applied to the control gate and the bit line is grounded, causing electrons from the channel of a storage element to be injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the storage element is raised so that the storage element is in a programmed state. More information about such programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique For Non-Volatile Memory,” and in U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory,” both of which are incorporated herein by reference in their entirety.
However, during programming of a selected storage element, neighboring storage elements may have their charge states altered due to field effect coupling, as described in U.S. Pat. No. 5,867,429, titled “High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates”, and incorporated herein by reference. Generally, with field effect coupling, there is a shift in a storage element's threshold voltage due to a change in the amount of charge stored in neighboring storage elements. For example, a storage element on a given word line can be affected by capacitive coupling from storage elements on the same word line and on neighboring word lines. The coupling, which is strongest from the adjacent storage elements, causes the threshold voltage of a previously programmed storage element to be shifted higher. The threshold voltage distribution of a set of storage elements is likewise widened. This is undesirable, especially for multi-level storage elements, in which tighter threshold voltage distributions are advantageous.